Analysis and Synthesis of Logic Functions using Multiplexers            

Introduction

About the Experiment

This experiment enables a student to learn

  • How to realize functionality of Dual 4 Line to 1 Line Multiplexer using 74153 IC
  • How Dual 4 Line to 1 Line Multiplexer select the particular input to be sent to the output IY{1 = 1, 2}.
  • How Each of the strobe signals IG {I = 1, 2} acts as an enable signal for the corresponding 4-to-1 M multiplexer.
  • How to realize functionality of Quad 2 Line to 1 Line Multiplexer using 74157 IC
  • How Quad 2 Line to 1 Line Multiplexer select the particular input to be sent to the output IY{1 = 1, 2, 3, 4}.
  • How the strobe signal acts as an enable signal for each of the four 4-to-1 M multiplexers.

Theory

74153 is a dual 4 line-to-1 line multiplexer. It has the schematic representation shown in Fig 1. Selection lines A and B select the particular input to be multiplexed and applied to the output IY{1 = 1, 2}.Each of the strobe signals IG {I = 1, 2} acts as an enable signal for the corresponding multiplexer.Figure 2(a) & 2(b) shows the multiplex function of 74153 in terms of select lines. Note that each of the on-chip multiplexers act independently from the other, while sharing the same select lines A and B.

Figure 1(74153)

Strobe Select Lines Outputs
1G A B 1Y
1 x x 0
0 0 0 1C0
0 0 1 1C1
0 1 0 1C2
0 1 1 1C3

Figure 2(a) x:don't care state

Strobe Select Lines Outputs
2G A B 2Y
1 x x 0
0 0 0 2C0
0 0 1 2C1
0 1 0 2C2
0 1 1 2C3

Figure 2(b) x:don't care state


The above circuit diagram shows the detail gate level structure of 74153(Dual 4 line to 1 line Multiplexer)

74157 is a quad 2 line-to-1 line multiplexer. It has the schematic representation shown in Fig 3. Select line select the particular input to be multiplexed and applied to the output IY{1 = 1, 2, 3, 4}. Strobe signal acts as an enable signal for each of the four multiplexers. Figure 4(a) & 4(b) & 4(c) & 4(d) shows the multiplex function of 74157 in terms of select lines. Note that each of the on-chip multiplexers act independently from the other, while sharing the same select line.

Figure 3(74157)

Strobe Select Inputs Outputs
A1 B1 1Y
H x x x L
L L L x L
L L H x H
L H x L L
L H x H H

Figure 4(a) x:don't care state

Strobe Select Inputs Outputs
A2 B2 2Y
H x x x L
L L L x L
L L H x H
L H x L L
L H x H H

Figure 4(b) x:don't care state

Strobe Select Inputs Outputs
A3 B3 3Y
H x x x L
L L L x L
L L H x H
L H x L L
L H x H H

Figure 4(c) x:don't care state

Strobe Select Inputs Outputs
A4 B4 4Y
H x x x L
L L L x L
L L H x H
L H x L L
L H x H H

Figure 4(d)x:don't care state

The above circuit diagram shows the detail gate level structure of 74157(Quad 2 line to 1 line Multiplexer)

74151 is a 8 line-to-1 line multiplexer. It has the schematic representation shown in Fig 5. Three select lines(A,B,C) select the particular input to be multiplexed and applied to the output Y, Y is the inverted output of the original outpu(Y). Strobe signal or Enable signal should be low to ensure proper multiplexing operation.If Enable is made high,then the output Y will always be low irrespective of any logic levels asserted by select lines A, B, C and the eight inputs.

An 8-to-1 Multiplexer can be used to implement any 3-variable switching function.

For example, consider the function

F (A,B,C) = &Sigma m (0,3,5)

Then the inputs D0, D3 and D5 should be set to logic 1 while the remaining five inputs we set to logic '0'.

Thus, for A = 0, B = 0, C = 0 Y = D0 = '1'

for A = 0, B = 1, C = 1, Y = D1, = '1'

for A = 1, B = 0, C = 1, Y = D5, = '1'

For the remaining combination of A, B, C Y = '0'.

Figure 5(a)

Strobe Select Lines Inputs Outputs
A B C D0 D1 D2 D3 D4 D5 D6 D7 Y Y
H X X X X X X X X X X X L H
L L L L H X X X X X X X H L
L L L L L X X X X X X X L H
L L L H X H X X X X X X H L
L L L H X L X X X X X X L H
L L H L X X H X X X X X H L
L L H L X X L X X X X X L H
L L H H X X X H X X X X H L
L L H H X X X L X X X X L H
L H L L X X X X H X X X H L
L H L L X X X X L X X X L H
L H L H X X X X X H X X H L
L H L H X X X X X L X X L H
L H H L X X X X X X H X H L
L H H L X X X X X X L X L H
L H H H X X X X X X X H H L
L H H H X X X X X X X L L H

Figure 5(b): Truth Table