Analysis and Synthesis of Multi-bit Sequential Circuits using Shift Register

INSTRUCTION

  1. Apply \(V_{CC}\) , so that "clock start" button for the clock pulse will be enabled (CP1) . Apply low level voltage to ground(GND) .
  2. Next, apply low voltage to the mode control input (S) and start the clock pulse(CP1). Now the serial input Ds is enabled. The input at \(D_{s}\) will be shifted right to the outputs \(Q_{0}\), \(Q_{1}\), \(Q_{2}\), \(Q_{3}\) at negetive transition of CP1. All the parallel inputs \(P_{0}\), \(P_{1}\), \(P_{2}\), \(P_{3}\) are disabled
  3. Now apply high voltage to \(D_{s}\) input and set no of clock pulses to 1. See that the input will be shifted to \(Q_{0}\) output at negetive clock edge.
  4. Next, start the clock pulse again. See the input is now shifted to the output \(Q_{1}\).
  5. Again start the clock pulse and see the input is shifted to the output \(Q_{2}\)
  6. Start the clock pulse again. Now see that at fouth clock pulse input is shifted to the output \(Q_{3}\).
  7. Apply high voltage to the mode control input (s). Now the "Clock Start" button for the second clock pulse (CP2) is enabled. Parallel inputs \(P_{0}\), \(P_{1}\), \(P_{2}\), \(P_{3}\) are enabled. These parallel inputs are directly loaded to the outputs \(Q_{0}\), \(Q_{1}\), \(Q_{2}\), \(Q_{3}\) respectively.
  8. Start the clock pulse (CP2).After generation of some clock pulses stop the clock by clicking in "Clock Stop" button.
  9. Now apply high voltage to \(P_{0}\) input and set no of clock pulses to 1. See \(P_{0}\) input is directly loaded to the output \(Q_{0}\).
  10. Next, apply high voltage to \(P_{1}\) and start the clock pulse. \(P_{1}\) input is directly loaded to \(Q_{1}\).
  11. Next, apply high voltage to \(P_{2}\) and start the clock pulse. \(P_{2}\) input is directly loaded to \(Q_{2}\).
  12. Now apply high voltage to \(P_{3}\) and start the clock pulse. \(P_{3}\) input is directly loaded to \(Q_{3}\).
  13. Click button "Plot" to see the graphical representation of shift register.
  14. Note: Red symbolize as Low (L), Green symbolize as High(H).

TRUTH TABLE

Operating mode Inputs Outputs
\(S_{}\) \(CP_{1}\) \(CP_{2}\) \(D_{s}\) \(P_{n}\) \(Q_{0}\) \(Q_{1}\) \(Q_{2}\) \(Q_{3}\)
Shift \(L_{}\) # \(X_{}\) \(I_{}\) \(X_{}\) \(L_{}\) \(Q_{0}\) \(Q_{1}\) \(Q_{2}\)
\(L_{}\) # \(X_{}\) \(H_{}\) \(X_{}\) \(H_{}\) \(Q_{0}\) \(Q_{1}\) \(Q_{2}\)
Parallel Load \(H_{}\) \(X_{}\) # \(X_{}\) \(P_{n}\) \(P_{0}\) \(P_{1}\) \(P_{2}\) \(P_{3}\)

CIRCUIT DIAGRAM

shift register image